This invention relates to electrostatic discharge protection, and more particularly, to circuitry for protecting sensitive circuits from damage due to electrostatic discharge events.
Integrated circuits are often exposed to potentially damaging electrostatic charges. For example, a wafer of integrated circuits may be exposed to electric charges during fabrication. Such charges may arise from the use of plasma etching techniques or other processes that produce charged particles. As another example, a packaged integrated circuit may be exposed to electrostatic charges when a worker inadvertently touches exposed pins on the circuit's package or when the package becomes charged electrostatically due to movement of the package in a tray.
These electrostatic charges can damage sensitive circuitry. For example, transistors and other electrical devices on an integrated circuit can be damaged when exposed to excessive currents.
To reduce the impact of electrostatic charges on sensitive circuitry, integrated circuits may be provided with electrostatic discharge protection circuitry. Conventional electrostatic discharge protection circuitry may not, however, be compatible with the type of sensitive circuitry that is being protected or may not protect circuits adequately against certain types of electrostatic events.
It would therefore be desirable to provide improved circuitry for protecting integrated circuits against the harmful effects of electrostatic discharge.